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| CCD Linear Image Sensor MN3610H 2048-Bit High-Responsivity CCD Linear Image Sensor s Overview The MN3610H is a 2048-pixel high sensitivity CCD linear image sensor combining photo-sites using low dark output floating photodiodes and CCD analog shift registers for read out. It provides large output at a high S/N ratio for visible light inputs over a wide range of wavelength. s Pin Assignments 1 OS DS VDD oR o1B o1A NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 2048 (Top View) C20 s Features * 2048 floating photodiodes and n-channel buried type CCD shift registers for read out are integrated in a single chip. * Use of photodiodes with a new structure has made the dark output voltage very low. * All the input pulses can be driven by CMOS 5V-type logics. * Has a smooth spectral characteristics that is close to the sensitivity of the human eye in the entire visible region. 22 21 20 19 18 17 16 15 14 13 12 VSS o SG o 2B o 2A NC NC NC NC NC NC NC * Large signal output of typically 2000mV at saturation can be obtained. * Since a compensation output pin (DS) is provided in addition to the signal output pin (OS), it is possible to obtain a signal with a high S/N ratio by carrying out differential amplification of the OS and DS outputs. * Operation with a single +12V positive power supply. WDIP022-G-0470 s Application * Graphic and character read out in fax machines, image scanners, etc. * Measurement of position and dimensions of s Block Diagram VSS 22 objects. o SG 21 o 2B 20 o 2A 19 2 1 21 21 2 B1 B2 B3 2 1 21 21 21 2 1 B 51 B 52 D1 D2 D3 1 2 3 4 5 1 21 2 1 21 2 1 21 2045 2046 2047 2048 D4 D5 D6 D7 D8 1 2 12121 1 21 21 21 21 2 21 21 21 21 21 2 B1 to B52 : Black reference pixels D 1 2 3 4 5 6 D1 to D8 : Dummy invalid pixels OS DS VDD o R o 1B o 1A CCD Linear Image Sensor s Absolute Maximum Ratings (Ta=25C, VSS=0V) Parameter Power supply voltage Input pin voltage Output pin voltage Operating temperature range Storage temperature range Symbol VDD VI VO Topr Tstg Rating - 0.3 to +15 - 0.3 to +15 - 0.3 to +15 -2 5 to + 60 -40 to +100 MN3610H Unit V V V C C s Operating Conditions * Voltage conditions (Ta=-25 to +60C, VSS=0V) Parameter Power supply voltage CCD shift register clock High level CCD shift register clock Low level Shift gate clock High level Shift gate clock Low level Reset gate clock High level Reset gate clock Low level Symbol VDD Vo H Vo L VSH VSL VRH VRL Condition min 11.4 4.5 0 4.5 0 4.5 0 typ 12.0 5.0 0.2 5.0 0.2 5.0 0.2 max 13.0 5.5 0.5 5.5 0.5 5.5 0.5 Unit V V V V V V V * Timing conditions (Ta=-20 to +60C) Parameter Shift register clock frequency Reset clock frequency Shift register clock rise time Shift regisster clock fall time Shift clock rise time Shift clock fall time Shift clock set up time Shift clock pulse width Shift clock hold time Reset clock rise time Reset clock fall time Reset clock pulse width Reset clock hold time Symbol fC fR t Cr t Cf t Sr t Sf t Ss t Sw t Sh t Rr t Rf t Rw t Rh fC =1/2T See drive timing diagram. fR =1/T Condition min -- -- 0 0 0 0 0 200 0 0 0 40 100 typ 0.5 1.0 50 50 50 50 100 1000 100 15 15 250 125 max 2.5 5.0 100 100 100 100 -- -- -- 30 30 -- -- Unit MHz MHz ns ns ns ns ns ns ns ns ns ns ns s Electrical Characteristics * Clock input capacitance (Ta=-25 to +60C) Parameter Shift register clock input capacitance Shift register final stage clock input capacitance Reset clock input capacitance Shift clock input capacitance Symbol C1A ,C 2A C1B ,C2B CR CS VIN =12V f =1MHz Condition min -- -- -- -- typ 450 15 10 130 max 500 20 20 150 Unit pF pF pF pF * DC characteristics Parameter Power supply current Symbol IDD VDD =+12V Condition min -- typ 6 max 12 Unit mA * AC characteristics Parameter Signal output delay time Symbol t OS Condition min -- typ 50 max -- Unit ns MN3610H s Optical Characteristics CCD Linear Image Sensor to F=10). * Load resistance = 100k Ohms * These specifications apply to the 2048 valid pixels excluding the dummy pixels D1 to D6. Parameter Responsivity Photo response non-uniformity Odd/even bit non-uniformity Saturation output voltage Saturation exposure Dark signal output voltage Dark signal output non-uniformity Shift register total transfer efficiency Output impedance Dynamic range Signal output pin DC level Compensation output pin DC level Symbol R PRNU O/E VSAT SE VDRK DSNU STTE ZO DR VOS V DS Note 5 Note 6 Note 6 Note 6 Note 1 Note 2 Note 3 Note 3 Dark condition, see Note 4 Dark condition, see Note 4 Condition min 10.0 -- -- 1.5 0.10 -- -- 92 -- -- 3.5 3.5 -- typ 12.0 -- -- 2.0 0.17 0.4 0.2 -- -- 5000 4.5 4.5 20 max 14.0 10 3 -- -- 1.0 2.0 -- 1 -- 6.0 6.0 100 V V mV Unit V/lx*s % % V lx*s mV mV % k Signal and compensation output pin DC level difference VOS - VDS Note 1) The photo response non-uniformity (PRNU) is defined by the following equation, where Xave is the average output voltage of the 2048 valid pixels and x is the absolute value of the difference between Xave and the voltage of the maximum (or minimum) output pixel, when the surface of the photo-sites is illuminated with light having a uniform distribution over the entire surface. x x100 (%) PRNU= Xave The incident light intensity shall be 50% of the standard saturation light intensity. Note 2) The odd/even bit non-uniformity (O/E) is defined by the following equation, where Xave is the average output voltage of the 2048 valid pixels and Xn is the output voltage of the `n'th pixel, when the surface of the photo-sites is illuminated with light having a uniform distribution over the entire surface. | Xn-Xn+1 | n=1 x100 (%) 2047xX ave In other words, this is the value obtained by dividing the average of the output difference between the odd and even pixels by the average output voltage of all the valid pixels. The incident light intensity shall be 50% of the standard saturation light intensity. Note 3) The Saturation output voltage (VSAT) is defined as the output voltage at the point when the linearity of the photoelectric characteristics cannot be maintained as the incident light intensity is increased. (The light intensity of exposure at this point is called the saturation exposure.) Note 4) The dark signal output voltage (VDRK) is defined as the average output voltage of the 2048 pixels in the dark condition at Ta=25C and Tint=10ms. Normally, the dark output voltage doubles for every 8 to 10C rise in Ta, and is proportional to Tint. The dark signal output non-uniformity (DSNU) is defined as the difference between the maximum output voltage among all the valid pixels and VDRK in the dark condition at Ta=25C and Tint=10ms. O/E= VDRK DSNU Note 5) The dynamic range is defined by the following equation. VSAT VDRK Since the dark signal voltage is proportional to the accumulation time, the dynamic range becomes wider when the accumulation time is shorter. DR= 2047 CCD Linear Image Sensor MN3610H Note 6) The signal output pin DC level (VOS) and the compensation output pin DC level (VDS) are the voltage values shown in the following figure. OS V OS VSS VSS Reset feed through level DS VDS s Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Symbol OS DS VDD oR o1B o1A NC NC NC NC NC NC NC NC NC NC NC NC o2A o2B oSG VSS Signal output Compensation output Power supply Reset clock CCD Final stage clock (Phase 1) CCD Clock (Phase 1) Non connection Non connection Non connection Non connection Non connection Non connection Non connection Non connection Non connection Non connection Non connection Non connection CCD Clock (Phase 2) CCD Final stage clock (Phase 2) Shift gate clock Ground Pin name Condition Note) Connect all NC pins externally to VSS. s Construction of the Image Sensor The MN3610H can be made up of the three sections of--a) photo detector region, b) CCD transfer region (shift register), and c) output region. a) Photo detector region * The photoelectric conversion device consists of an 11m floating photodiode and a 3m channel stopper for each pixel, and 2048 of these devices are linearly arranged side by side at a pitch of 14m. * The photo detector's windows are 14m x 14m squares and light incident on areas other than these windows is optically shut out. * The photo detector is provided with 52 optically shielded pixels (black dummy pixels) which serve as the black reference. b) CCD Transfer region (shift register) * The light output that has been photoelectrically converted is transferred to the CCD transfer for each odd and even pixel at the timing of the shift clock (oSG). The optical signal electric charge transferred to this analog shift register is successively transferred out and guided to the output region. * A buried type CCD that can be driven by a two phase clock (o1, o2) is used for the analog shift register. c) Output region * The signal charge that is transferred to the output region is sent to the detector where impedance transformation is done using two source follower stages. * The DC level component and the clock noise component not containing optical signals are output from the DS pin. * By carrying out differential amplification of the two outputs OS and DS externally, it is possible to obtain an output signal with a high S/N ratio by reducing the clock noise, etc. MN3610H s Timing Diagram (1) I/O timing Integration Time (Tint.) CCD Linear Image Sensor o SG o1 o2 oR 1234 6 7 8 9 10 11 58 59 60 61 62 63 64 65 66 2110 2112 2114 2116 2111 2113 2115 DS OS 1234 6 7 8 B1 B2 B50 B52 B51 D1 D3 1 2 3 2047 2048D 4 Blank feed (for 8 pixels) Black reference pixel signal (for 52 pixels) D2 D5 D6 D7 D8 Note) Repeat the transfer pulses (cp) for more than 1060 periods. Valid pixel signal (for 2048 pixels) Invalid pixel signal (for 5 pixels) Invalid pixel signal (for 3 pixels) (2)Drive timing o1 t Cr o2 90% 50% 10% t Cf 90% 50% 10% t Rh 90% t Rf t RW 10% tRr T Reference level Signal output voltage 90% t Sr t Sf 90% oR o SG 10% 90% DS t OS OS o1 t Ss t SW t Sh s Graphs and Characteristics Spectral Response Characteristics 100 Under standard operating condition Relative responsivity (%) 80 60 40 20 0 400 500 600 700 Wavelength (nm) 800 |
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